Property specification language (PSL) - Verilog Tutorial

Property Specification Language (PSL) is a formal language used for hardware verification in Verilog designs. PSL enables designers to specify properties or conditions that must always hold true during simulation or synthesis, providing rigorous and exhaustive verification of hardware designs. In this tutorial, we will explore PSL and understand how to use it effectively for hardware verification.

Example: PSL Property for a FIFO

Let's begin with an example of a PSL property for a FIFO (First-In-First-Out) design to ensure that the FIFO is never full and empty simultaneously:


    module fifo (
        input wire clk,
        input wire reset,
        input wire write_en,
        input wire read_en,
        output wire data_out,
        output wire full,
        output wire empty
    );

    // FIFO implementation goes here...

    // PSL property to check that FIFO is never full and empty simultaneously
    property no_full_and_empty;
        @(posedge clk) disable iff (reset)
        (!(full && empty));
    endproperty

    // Assert the property
    assert property (no_full_and_empty);

    endmodule

Steps to Use PSL for Hardware Verification

Using PSL for hardware verification involves the following steps:

PSL Syntax: Understand the syntax and constructs of PSL, including the use of sequences, properties, and operators.
Property Specification: Define the properties or conditions that must hold true during simulation or synthesis, ensuring the correctness of the hardware design.
PSL Integration: Integrate PSL properties into the Verilog design code at appropriate locations to check specific conditions.
Simulation: Use simulation tools with PSL support to verify the PSL properties during simulation.
Synthesis: Synthesize the design with PSL properties to ensure that the specified properties are preserved in the synthesized hardware.
Formal Verification: Use formal verification tools to formally prove specific properties of the design.
Coverage Analysis: Analyze the PSL property coverage to ensure that critical properties have been exercised during verification.

Common Mistakes with PSL

Not fully understanding the PSL syntax and semantics, leading to incorrect property specifications.
Using overly complex or inefficient PSL properties, resulting in lengthy verification processes.
Ignoring formal verification tools for rigorous property proving.

Frequently Asked Questions

Q: What is the advantage of using PSL for hardware verification?
A: PSL provides formal verification capabilities, enabling rigorous and exhaustive verification of hardware designs.
Q: Can I use PSL with other hardware description languages?
A: Yes, PSL is not limited to Verilog and can be used with other hardware description languages like VHDL.
Q: How do PSL properties differ from Verilog assertions?
A: PSL properties provide formal verification capabilities, while Verilog assertions are used for simulation-based verification.
Q: Are there any free tools available for PSL-based verification?
A: Yes, there are free and open-source formal verification tools that support PSL, such as SymbiYosys and Yosys-SMTBMC.
Q: Can PSL properties be used for post-silicon validation?
A: Yes, PSL properties can be used for post-silicon validation to ensure the correctness of the fabricated hardware.

Summary

Property Specification Language (PSL) is a powerful formal language used for hardware verification in Verilog designs. By defining properties and conditions that must always hold true, PSL enables rigorous and exhaustive verification of hardware designs, providing designers with increased confidence in the correctness of their designs. By integrating PSL into the verification process, designers can achieve more robust and reliable hardware implementations for a wide range of applications.